MIC-3612是一款4端口RS-232/422/485 PCI 通信卡。它和PCI 2.1 bus规格兼容。MIC-3612提供4个过电压保护，RS-232/422/485端口满足用户需要。它有许多特色功能：高传输速度921.6 Kbps;4个独立的RS-232/422/485端口；可选的过电压保护等等。MIC-3612还带有高性能的128节 FIFO 16PCI954 UART以减少CPU的负荷。

特点

符合 PCI 2.1 规格

通讯速度可达 921.6 Kbps

4 端口 RS-232/422/485浪涌保护

128 字节标准的 16C954 UART

标准工业 CompactPCI® 3U 板尺寸

I/O 地址由 PCI 即插即用功能自动分配

OS 支持： Windows® 98/2000/XP, Linux, VxWorks

提高系统性能的中断状态寄存器

自动 RS-485 数据流控制

Tx/Rx LED 指示灯

规格

通讯 总线控制器: PLX9030

控制器UART: 16C954

数据位 5, 6, 7, 8

数据信号 TxD, RxD, RTS, CTS, DTR,DSR, DCD, RI, GND(用于 RS-232)

TxD, RxD, RTS, CTS(用于 RS-422)

DATA+, DATA- (用于 RS-485)

IRQ 所有端口使用由 PCI 即插即用功能分配的同一个 IRQ

校验 无校验，偶校验，奇校验

速率 (bps) 50 ~ 921.6 k

停止位 1, 1.5, 2

一般规格

PICMG 符合性 CompactPCI V2.0, R 3.0热插拔 V2.1, R 2.0

总线类型 CompactPCI V2.1

I/O 接口 DB 44孔型接口

尺寸(L x H) 160 x 100 mm (6.3" x 3.9"),带 3U/6U 把手

环境参数

工作温度 0 ~ 70° C (IEC68-2-1, 2)

储存温度 -20 ~ 80° C

工作湿度 5 ~ 95% RH, 无凝结 (IEC68-2-1, 2)

查看源码

 
 
#ifndef __VXMIC3612SIO_H 
#define __VXMIC3612SIO_H  
 
#ifdef __cplusplus 
extern "C" { 
#endif 
 
#define MIC_3612_DEVID (0X3612) 
#define MIC_3612_VENDORID (0x13fe) 
 
#define MIC3612_BOARD_MAX 0x4 
#define MIC3612_CHANNEL_NUM 0x4 
 
#define MIC3612_BAUD_DEF 9600 
#define MIC3612_INPUT_CLOCK 14745600 
 
#define MIC3612_MODE_NORMAL 0x0 
#define MIC3612_MODE_LOOPBACK 0x1 /*内部自环模式*/ 
 
#define MIC3612_CHANNELMODE_POLL 0x0 /*轮询模式*/ 
#define MIC3612_CHANNELMODE_INT 0x1 /*中断模式*/ 
 
#define MIC3612_RCVBUF_LEN 0x400 
#define MIC3612_STARTFLAG 0xaa 
#define MIC3612_READFLAG 0x55 
 
/* ioctl选项 */ 
 
#define BAUDRATE_SET 0 
#define BAUDRATE_GET 1  
#define SIOMODE_SET 2 
#define SIOMODE_GET 3 
#define AVAILMODES_GET 4 
#define DATAFORMAT_SET 5 
 
/* Register offsets from base address */ 
 
#define RBR 0x00 /* receiver buffer register */ 
#define THR 0x00 /* transmit holding register */ 
#define DLL 0x00 /* divisor latch */ 
#define IER 0x01 /* interrupt enable register */ 
#define DLM 0x01 /* divisor latch(MS) */ 
#define ISR 0x02 /* interrupt status register */ 
#define FCR 0x02 /* FIFO control register */ 
#define LCR 0x03 /* line control register */ 
#define MCR 0x04 /* modem control register */ 
#define LSR 0x05 /* line status register */ 
#define MSR 0x06 /* modem status register */ 
#define SCR 0x07 /* scratch register */ 
 
#define ICR 0x05 /* Indexed Control Register */ 
#define EFR 0x2 /* I/O: Extended Features Register 访问该寄存器的时候，LCR=0xBF */ 
 
/* Specific Registers */ 
 
#define ASR 0x01 /* Additional Status Register */ 
#define RFL 0x03 /* Number of characters in the receiver FIFO */ 
#define TFL 0x04 /* Number of characters in the transmitter FIFO */ 
 
 
 
/* The ICR registers */ 
#define UART_ACR 0x00 /* Additional Control Register */ 
#define UART_CPR 0x01 /* Clock Prescalar Register */ 
#define UART_TCR 0x02 /* Times Clock Register */ 
#define UART_CKS 0x03 /* Clock Select Register */ 
#define UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */ 
#define UART_RTL 0x05 /* Receiver Interrupt Trigger Level */ 
#define UART_FCL 0x06 /* Flow Control Level Lower */ 
#define UART_FCH 0x07 /* Flow Control Level Higher */ 
#define UART_ID1 0x08 /* ID #1 */ 
#define UART_ID2 0x09 /* ID #2 */ 
#define UART_ID3 0x0A /* ID #3 */ 
#define UART_REV 0x0B /* Revision */ 
#define UART_CSR 0x0C /* Channel Software Reset */ 
#define UART_NMR 0x0D /* Nine-bit Mode Register */ 
#define UART_CTR 0xFF 
 
 
/* Line Status Register */ 
 
#define LSR_DR 0x01 /* Data Ready */ 
#define RxCHAR_AVAIL LSR_DR 
#define LSR_OE 0x02 /* Overrun Error */ 
#define LSR_PE 0x04 /* Parity Error */ 
#define LSR_FE 0x08 /* Framing Error */ 
#define LSR_BI 0x10 /* Received Break Signal */ 
#define LSR_THRE 0x20 /* Transmit Holding Register Empty */ 
#define LSR_TEMT 0x40 /* THR and FIFO empty */ 
#define LSR_FERR 0x80 /* Parity, Framing error or break in FIFO */ 
 
 
 
 
/* Line Control Register values */ 
 
#define CHAR_LEN_5 0x00 
#define CHAR_LEN_6 0x01 
#define CHAR_LEN_7 0x02 
#define CHAR_LEN_8 0x03 
#define LCR_STB 0x04 /* Stop bit control (1.5/2)*/ 
#define ONE_STOP 0x00 /* One stop bit! */ 
#define LCR_PEN 0x08 /* Parity Enable */ 
#define PARITY_NONE 0x00 
#define LCR_EPS 0x10 /* Even Parity Select */ 
#define LCR_SP 0x20 /* Force Parity */ 
#define LCR_SBRK 0x40 /* Start Break */ 
#define LCR_DLAB 0x80 /* Divisor Latch Access Bit */ 
#define DLAB LCR_DLAB 
 
 
/* Modem Control Register */ 
 
#define MCR_DTR 0x01 /* state of DTR output */ 
#define DTR MCR_DTR 
#define MCR_RTS 0x02 /* state of RTS output */ 
#define MCR_OUT1 0x04 /* UNUSED in OX16954 */ 
#define MCR_INT 0x08 /* Int Mode */ 
#define MCR_LOOP 0x10 /* Enable Loopback mode */ 
 
/* 
 * The 16C950 Additional Control Reigster 
 */ 
#define UART_ACR_RXDIS 0x01 /* Receiver disable */ 
#define UART_ACR_TXDIS 0x02 /* Receiver disable */ 
#define UART_ACR_DSRFC 0x04 /* DSR Flow Control */ 
#define UART_ACR_TLENB 0x20 /* 950 trigger levels enable */ 
#define UART_ACR_ICRRD 0x40 /* ICR Read enable */ 
#define UART_ACR_ASREN 0x80 /* Additional status enable */ 
 
#define UART_EFR_ECB 0x10 /* Enhanced control bit */ 
 
/* FIFO Control Register */ 
 
#define FCR_EN 0x01 /* FIFO Enable */ 
#define FIFO_ENABLE FCR_EN 
#define FCR_RXCLR 0x02 /* Rx FIFO Clear */ 
#define RxCLEAR FCR_RXCLR 
#define FCR_TXCLR 0x04 /* Tx FIFO Clear */ 
#define TxCLEAR FCR_TXCLR 
#define FCR_DMA 0x08 /* FIFO Mode Control */ 
#define FCR_RXTRIG_L 0x40 /* FIFO Trigger level Low */ 
#define FCR_RXTRIG_H 0x80 /* FIFO Trigger level High */ 
 
/* Interrupt Enable Register */ 
 
#define IER_ERDAI 0x01 /* Enable Rx Data Available Int */ 
#define RxFIFO_BIT IER_ERDAI 
#define IER_ETHREI 0x02 /* Enable THR Empty Int */ 
#define TxFIFO_BIT IER_ETHREI 
#define IER_ELSI 0x04 /* Enable Line Status Int */ 
#define Rx_BIT IER_ELSI 
#define IER_EMSI 0x08 /* Enable Modem Status Int */ 
 
/* Interrupt Statis Register */ 
 
#define ISR_IP 0x01 /* Interrupt Pending */ 
#define ISR_ID 0x0E /* Interrupt source mask */ 
#define ISR_RLS 0x06 /* Rx Line Status Int */ 
#define Rx_INT ISR_RLS 
#define ISR_RDA 0x04 /* Rx Data Available */ 
#define RxFIFO_INT ISR_RDA 
#define ISR_THRE 0x02 /* THR Empty */ 
#define TxFIFO_INT ISR_THRE 
#define ISR_MSTAT 0x00 /* Modem Status Register Int */ 
#define ISR_TIMEOUT 0x0C /* Rx Data Timeout */ 
 
typedef struct ox16954_chan /* OX16954_CHAN */ 
{ 
 
    BOOL bInit; 
    UINT32 ulBaseAddr; /* ST16954 registers baseaddr*/ 
    UINT8 level; /* Interrupt level for this device */ 
    BOOL b485; /* channel is 485/422*/ 
    UINT8 ier; /* copy of IER */  
    UINT8 lcr; /* copy of LCR */ 
    UINT8 acr; /* copy of ACR */ 
    UINT16 fifosize; /* fifo size */ 
    UINT8 mode; /* 0-normal mode; 1-loopback mode */ 
    UINT32 channelMode; /* such as INT, POLL modes */ 
    UINT32 baudRate; /* the current baud rate */ 
    UINT32 xtal; /* UART clock frequency */ 
    SEM_ID rxSem; /* 中断接收模式下的信号量*/ 
    UINT8 rBuf[MIC3612_RCVBUF_LEN]; /*under int mode,receive data buffer*/ 
    UINT32 ulWritePos; /*指向下个写位置*/ 
    UINT32 ulReadPos; /*指向下个读位置*/ 
 
} OX16954_CHAN_ST; 
 
typedef struct  
{ 
    char dataBits; /* 数据位5，6，7，8 */ 
    char stopBits; /* 停止位1，2 */ 
    char parityBits; /* 奇偶校验位 0-没有 1-奇校验 2-偶校验 */ 
} DATAFORMAT_ST; 
 
extern STATUS Hwa_MIC3612_Init(unsigned char uchBoardNo, unsigned char uchChanNo); 
extern STATUS Hwa_MIC3612_Ioctl(unsigned char uchBoardNo, unsigned char uchChanNo, int request, int arg); 
extern STATUS Hwa_MIC3612_Send(unsigned char uchBoardNo, unsigned char uchChanNo, char *pszData, unsigned long ulCount); 
extern STATUS Hwa_MIC3612_Rcv(unsigned char uchBoardNo, unsigned char uchChanNo, unsigned char *pszRcvBuf, unsigned long *pszLen); 
extern STATUS Hwa_MIC3612_IntRcv(unsigned char uchBoardNo, unsigned char uchChanNo, unsigned char *pszRcvBuf, unsigned long *pulLen); 
extern STATUS Hwa_MIC3612_IntConfig(unsigned char uchBoardNo, unsigned char uchChanNo, unsigned char Rlevel); 
extern STATUS Hwa_MIC3612_Exit(unsigned char uchBoardNo, unsigned char uchChanNo); 
 
#ifdef __cplusplus 
} 
#endif 
  
#endif 
 
 

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